Micron Technology, Inc. vs Tessera, Inc., No. 2:05-cv-00319 (E.D. Tex. July 13, 2006)

2Both the ‘849 and ‘325 patents relate to means for connecting multiple semiconductor die onto a polymide substrate where the substrate functions as both a lead frame connection for the semiconductor die and as a printed circuit board.

Applicable Law

“It is a ‘bedrock principle’ of patent law that ‘the claims of a patent define the

invention to which the patentee is entitled the right to exclude.” Phillips v. AWH Corp., 415 F.3d 1303, 1312 (Fed. Cir. 2005) (en banc) (quoting Innova/Pure Water Inc. v. Safari Water Filtration Sys., Inc., 381 F.3d 1111, 1115 (Fed. Cir. 2004)). In claim construction, courts examine the patent’s intrinsic evidence to define the patented invention’s scope. See id.; C.R. Bard, Inc. v. U.S. Surgical Corp., 388 F.3d 858, 861 (Fed. Cir. 2004); Bell Atl. Network Servs., Inc. v. Covad Communications Group, Inc., 262 F.3d 1258, 1267 (Fed. Cir. 2001). This intrinsic evidence includes the claims themselves, the specification, and the prosecution history. See Phillips, 415 F.3d at 1314; C.R. Bard, Inc., 388 F.3d at 861. Courts give claim terms their ordinary and accustomed meaning as understood by one of ordinary skill in the art at the time of the invention in the context of the entire patent. Phillips, 415 F.3d at 1312-13; Alloc, Inc. v. Int’l Trade Comm’n, 342 F.3d 1361, 1368 (Fed. Cir. 2003).

The claims themselves provide substantial guidance in determining the meaning

of particular claim terms. Phillips, 415 F.3d at 1314. First, a term’s context in the asserted claim can be very instructive. Id. Other asserted or unasserted claims can also aid in determining the claim’s meaning because claim terms are typically used consistently throughout the patent. Id. Differences among the claim terms can also assist in understanding a term’s meaning. Id. For example, when a dependent claim adds a

3limitation to an independent claim, it is presumed that the independent claim does not include the limitation. Id. at 1314-15. Claims “must be read in view of the specification, of which they are a part.” Id.

(quoting Markman v. Westview Instruments, Inc., 52 F.3d 967, 978 (Fed. Cir. 1995)). “[T]he specification ‘is always highly relevant to the claim construction analysis. Usually, it is dispositive; it is the single best guide to the meaning of a disputed term.’” Id. (quoting Vitronics Corp. v. Conceptronic, Inc., 90 F.3d 1576, 1582 (Fed. Cir. 1996)); Teleflex, Inc. v. Ficosa N. Am. Corp., 299 F.3d 1313, 1325 (Fed. Cir. 2002). This is true because a patentee may define his own terms, give a claim term a different meaning than the term would otherwise possess, or disclaim or disavow the claim scope. Phillips, 415 F.3d at 1316. In these situations, the inventor’s lexicography governs. Id. Also, the specification may resolve ambiguous claim terms “where the ordinary and accustomed meaning of the words used in the claims lack sufficient clarity to permit the scope of the claim to be ascertained from the words alone.” Teleflex, Inc., 299 F.3d at 1325. But, “although the specification may aid the court in interpreting the meaning of disputed claim language, particular embodiments and examples appearing in the specification will not generally be read into the claims.” Comark Communications, Inc. v. Harris Corp., 156 F.3d 1182, 1187 (Fed. Cir. 1998); see also Phillips, 415 F.3d at 1323. The prosecution history is another tool to supply the proper context for claim construction because a patent applicant may also define a term in prosecuting the patent. Home Diagnostics, Inc., v. Lifescan, Inc., 381 F.3d 1352, 1356 (Fed. Cir. 2004) (“As in the case of the specification, a patent applicant may define a term in prosecuting a patent.”).

4Although extrinsic evidence can be useful, it is “less significant than the intrinsic

record in determining ‘the legally operative meaning of claim language.’” Phillips, 415 F.3d at 1317 (quoting C.R. Bard, Inc., 388 F.3d at 862). Technical dictionaries and treatises may help a court understand the underlying technology and the manner in which one skilled in the art might use claim terms, but technical dictionaries and treatises may provide definitions that are too broad or may not be indicative of how the term is used in the patent. Id. at 1318. Similarly, expert testimony may aid a court in understanding the underlying technology and determining the particular meaning of a term in the pertinent field, but an expert’s conclusory, unsupported assertions as to a term’s definition is entirely unhelpful to a court. Id. Generally, extrinsic evidence is “less reliable than the patent and its prosecution history in determining how to read claim terms.” Id.

The Terms

The ‘849 and ‘325 Patents Proceeding on two separate theories, Tessera argues that the preambles to Claim 1 of the ‘849 and ‘325 patents limit those claims.¹ Tessera’s first theory is that these claims were written in Jepson form because they “first describe the scope of the prior art and then claim an improvement of the prior art.” Dow Chem. Co. v. Sumitomo Chem. Co., Ltd., 257 F.3d 1364 (Fed. Cir. 2001); 37 C.F.R. § 1.75(e). Alternatively, Tessera argues that the preambles are limiting because they recite essential structure that is important to

5the invention or necessary to give meaning to the claim. NTP, Inc. v. Research In Motion, Ltd., 418 F.3d 1282, 1305-06 (Fed. Cir. 2005), cert. denied, ---U.S.---, 126 S.Ct. 1174, 163 L.Ed.2d 1141 (2006). The Court finds that both preambles are limiting, but were not written in Jepson form. 37 C.F.R. § 1.75(e) sets forth the requirements for Jepson claims, and provides: Where the nature of the case admits, as in the case of an improvement, any independent claim should contain in the following order: (1) a preamble comprising a general description of all the elements or steps of the claimed combination which are conventional or known, (2) a phrase such as “wherein the improvement comprises,” and (3) those elements, steps and/or relationships which constitute that portion of the claimed combination which the applicant considers as the new or improved portion. Courts rely on Rule § 1.75(e)(1) when analyzing Jepson issues. See Epcon Gas

Systems, Inc. v. Bauer Compressors, Inc., 279 F.3d 1022, 1029 (Fed.Cir. 2002); Kegel Co. v. AMF Bowling, Inc., 127 F.3d 1420, 1426 (Fed.Cir. 1997). In a Jepson claim, the “preamble defines not only the context of the claimed invention, but also its scope.” Rowe v. Dror, 112 F.3d 473, 479 (Fed. Cir. 1997). By employing the Jepson form the patentee evidences the intention “to use the preamble to define, in part, the structural elements of his claimed invention.” Epcon Gas, 279 F.3d at 1029; Rowe, 112 F.3d at 479; Kegel, 127 F.3d at 1426. Rule § 1.75(e) and the associated case law require that Jepson claims contain

specific information in a narrowly defined form, and the Court is aware of no exceptions to these requirements. In arguing that Claim 1 of the ‘325 and ‘849 patents are Jepson claims, Tessera seeks to impermissibly relax these requirements. Tessera argues that the preambles were drafted in Jepson form because the

preamble language corresponds with prior art depicted in Figure 2 of the patent, and

6because the prior art references in the preamble are further described in the specification. However, the preamble of a Jepson claim must do more than refer to prior art that is more fully described elsewhere in the patent. Rule § 1.75(e)(1) requires that the preamble set forth a “general description all of the elements or steps of the claimed combination which are conventional or known.” Tessera seems to suggest that a preamble written in Jepson form need only refer to prior art to satisfy Rule § 1.75(e)(1). The Court disagrees. The preamble of a Jepson claim is drafted to “define, in part, the structural

elements of [the] claimed invention.” Epcon Gas, 279 F.3d at 1029; Rowe, 112 F.3d at 479; Kegel, 127 F.3d at 1426. Therefore, it is reasonable to require that the preamble set forth the elements or steps of the prior art that are improved upon so that the public may be fairly notified of the scope of the invention. Tessera cites no authority to support its argument that a preamble may be written in Jepson form if what is described in the preamble is described elsewhere in the specification as prior art, and the Court sees no reason to so interpret Rule § 1.75(e)(1). However, even assuming the preambles of the ‘849 and ‘325 comported with Jepson form, these claims lack the necessary transitional phrase indicating that the subsequent language comprises an improvement over the previously stated prior art. The preambles at issue conclude with the phrase “characterized by,” but Rule §

1.75(e)(2) requires that Jepson claims employ “a phrase such as ‘wherein the improvement comprises’ (emphasis added).” Although the phrase “such as” offers some leeway to the patentee, Tessera cites no authority to suggest the phrase “characterized by” satisfies Rule § 1.75(e)(2). The caselaw reflects some variation in the phrases used in Jepson claims, but they all communicate that the subsequent claim language constitutes

7an improvement. Neutrik AG v. Switchcraft, Inc., 31 Fed.Appx. 718, 720 (“the improvement comprising”); Epcon Gas, 279 F.3d at 1029, 1030 (“the improvement wherein”); Dow Chemical v. Sumitomo Chemical Co., Ltd., 257 F.3d 1364 (“the improvement which comprises”); DeMarini Sports, Inc. v. Worth, Inc., 239 F.3d 1314, 1318 (“an improvement comprising”); Kegel, 127 F.3d at 1426, 1423 (“the improvement comprising”) Rowe, 112 F.3d at 476 (“the improvement comprising”). All of these phrases communicate that the preceding language described prior art² and the subsequent language describes an improvement over that prior art. The phrase “characterized by” without more, is insufficient to satisfy Rule § 1.75(e)(2) because it fails to communicate that the subsequent language comprises an improvement over the previously stated elements or steps of prior art. As stated above, the narrowly defined Jepson form must be followed closely so that the public may be notified of the scope of the invention. Therefore, the Court cannot find that Claim 1 of either the ‘849 or the ‘325 patents is written in Jepson form.³ The Court will now address whether the preambles are limiting without regard to

Jepson form. When limitations in the body of a patent claim rely upon, and derive antecedent basis from, the claim preamble, the preamble may act as a necessary component of the claimed invention. Bicon, Inc. v. Straumann Co., 441 F.3d 945, 952 (Fed. Cir. 2006). In order to be limiting, the preamble must recite essential structure that

8is important to the invention or necessary to give meaning to the claim. Id. citing NTP, Inc. v. Research In Motion, Ltd., 418 F.3d 1282, 1305-06 (Fed. Cir. 2005), cert. denied, ---U.S.---, 126 S.Ct. 1174, 163 L.Ed.2d 1141 (2006). However, a preamble is not considered limiting “where a patentee defines a structurally complete invention in the claim body and uses the preamble only to state a purpose or intended use for the invention.” Rowe, 112 F.3d at 478 (Fed. Cir. 1997). In the ‘325 preamble, the phrase “a memory array in which a plurality of memory

circuit devices are arranged” is limiting because “memory array” and “memory circuit devices” provide antecedent basis for “the memory array” and “the memory devices” in part (e) of the body of Claim 1. 8:39-40; 9:7. Further, the phrase provides essential structure to the invention not set forth in the body of the claim. Bicon, Inc., 441 F.3d at 952. However, the remainder of the preamble is not limiting because it describes the claimed invention’s purpose or intended use, rather than describing essential structure. See 8:40-47; Rowe, 112 F.3d at 478. This segment of the preamble describes how the arrangement of memory devices may allow memory information to be obtained, but it does not describe any essential structure. By contrast, the entire ‘849 preamble is limiting because it recites essential structure and provides antecedent basis for part (b) of the body of Claim 1. See 9:5,7, and 14. The ‘328 Patent Conductive leads for electrically coupling with an electronic device, wherein said conductive leads electrically couple with said conductive traces There are several points of contention concerning the construction of this claim language, and the Court will address them individually. To begin with, Tessera argues

9that the entire phrase should be construed, whereas Micron contends only “conductive leads” requires construction.⁴ The Court agrees with Micron that only the phrase “conductive leads” should be construed. For the purposes of this discussion, the disputed claim language can be roughly

broken up into three parts. First, “conductive leads,” are identified, then the relationship between the “conductive leads” and the “electronic device” is described, and finally the relationship between the “conductive leads” and the “conductive traces” is described. In each relationship, the “conductive leads” “electrically couple” or are “electrically coupling,” with the “conductive traces” and “electronic device,” respectively. Properly understood, the entire phrase describes “conductive leads” acting as electrically conductive bridges between the “conductive traces” and the “electronic device.” That understanding may be gained from the plain and ordinary meaning of the language, and even if it were not, the Court would not adopt Tessera’s construction because it offers no more guidance than the claim language itself. Tessera’s construction tracks the three part structure described above. In

describing the relationship between “conductive leads” and “an electronic device,” Tessera’s construction provides that “conductive leads” are “used as input/output (I/O) for connecting the package body to an external device.” Compare 8:1-2 (“conductive leads for electronically coupling with an electronic device.”). Essentially, Tessera substitutes “connecting” for “electronically coupling,” which would not offer much

10assistance to a juror. See Sulzer Textil A.G. v. Picanol N.V., 358 F.3d 1356, 1366 (Fed. Cir. 2004). The construction goes on to say that “[t]he conductive leads are connected to the

conductive traces (emphasis added)” and then clarifies that the purpose of that connection is “to provide an electrical current path between the leads and the traces.” Compare 8:2-3 (“conductive leads electronically couple to said conductive traces.”). Here, Tessera has broken up the phrase “electrically couple” into two phrases that are longer, but not significantly more helpful, than the phrase itself. Tessera’s construction is not incorrect or confusing, but it simply reorganizes the claim language without offering more guidance than the claim language itself, which makes Tessera’s construction unhelpful, and therefore, improper. Sulzer, 358 F.3d at 1366. The Court will now address the parties’ arguments regarding the construction of

“conductive leads.”⁵ The basic disagreement concerns Tessera’s requirement that “conductive leads” be “long and thin, not shaped as a mass.”⁶ Micron insists that the patent does not restrict the physical shape or size of the “conductive leads,” but Tessera argues that Figures 2 and 3 depict “conductive leads” as long and thin, and further argues that one skilled in the art at the time the patent was issued would understand “conductive leads” to be “long and thin, not shaped as a mass.” However, the claim language does not explicitly support such a limitation, nor do the specification or extrinsic evidence compel the conclusion that “conductive leads” must take on any particular physical form.

11Claim 11 recites all of the components comprising the logic component, and

describes the pathway along which signals will travel between the electrical device and the semiconductor die. 7:29-32; 8:1-3 (describing “a second shelf having conductive traces thereon…wherein said traces couple with bond pads on the semiconductor die…conductive leads for electrically coupling with an electronic device, wherein said conductive leads electrically couple with said conductive traces.”). The “conductive leads” occupy a portion of that pathway, but their physical characteristics are not mentioned; only the function of the “conductive leads” as a link in the chain between the semiconductor die and the device is referenced. Therefore, a proper understanding of the claim language requires emphasis on the role of the “conductive leads” rather than their form. The specification implicitly refers to the “conductive leads” only three times,

calling them “input/output (I/O) leads” or just “I/O leads.” 2:24-26; 3:57-60; 4:45-48. Like the claim language, the specification focuses on the role “conductive leads” play, rather than their form. 2:24-26 (describing pads on the upper surface of the shelf being electrically coupled with conductive traces which attach to input/output (I/O) leads); 3:57-60 and 4:45-48 (describing coupling traces with I/O leads by means such as side brazing). Although Figures 2 and 3 depict “conductive leads” as long and thin, the Court declines to read that limitation into the claim. Burke, Inc., v. Bruno Indep. Living Aids, Inc., 183 F.3d 1334, 1341 (Fed. Cir. 1999). Tessera also argues that, without regard to how the term “leads” is used within the

patent, the meaning of “lead” was independently established at the time this patent issued, and any person skilled in the art would understand that “leads” were “long and

12thin, not shaped as a mass.” Micron disputes Tessera’s understanding, and the Court finds that the extrinsic evidence is not clear enough to support Tessera’s limitation. In support of its limitation, Tessera cites several patents issued around the time

the ‘328 patent was issued that contain embodiments where “leads” are shown as relatively long and thin. However, the fact that these leads are long and thin does not necessarily require that leads in general must be “long and thin, not shaped as a mass.” Tessera goes on to argue that the common understanding of “leads” excludes masses, bumps, or balls, pointing out that chip packages employing solder balls are known as “leadless packages” in the packaging industry. Micron counters that the common understanding of the word lead is much more inclusive, citing the 1989 Edition of the Electronic Materials Handbook, which defines “lead” as “[a] conductive path, usually self-supporting. That portion of an electrical component used to connect it to the outside world.” Electronic Materials Handbook, Vol. 1 at 1148 (1989). This definition is consistent with the patent’s treatment of the “conductive leads,” which was based primarily on the function of the “conductive leads” rather than their form. As the extrinsic evidence is conflicted, the Court is reluctant to rely on that evidence to justify Tessera’s more restrictive construction of “conductive leads.” Phillips, 415 F.3d 1318 (Noting that extrinsic evidence is “less reliable than the patent and its prosecution history in determining how to read claim terms.”) The last point of contention concerns Micron’s use of the phrase “on the outside

of the body.” Tessera objects to this language on the basis that “conductive leads” cannot be, at once, a part of a body and outside of that body. The Court disagrees with the logic underlying Tessera’s argument, and finds that the additional language is consistent with

13the claim language and specification. The claim language describes a self-contained die package with “conductive leads for coupling with an electronic device (emphasis added).” The electronic device is separate from the claimed logic component, and the leads couple the package with the outside device. Thus, in order to couple with a separate device, it is seemingly necessary that the leads be on the outside of the body. The specification reinforces this understanding of the placement of the conductive leads. 3:57-59 (“the traces have means for coupling with I/O leads on the outside of the ceramic body.”); 4:45-47 (“The traces have means for coupling with I/O leads on the outside of the body). Accordingly, the Court construes “conductive leads” to mean “conductive input/output (I/O) elements on the outside of the body.”

Conclusion

For the foregoing reasons, the Court interprets the claim language in this case in . the manner set forth above. For ease of reference, the Court’s claim interpretations are set forth in a table attached to this opinion.

So ORDERED and SIGNED this 13th day of July, 2006.

JOHN D. LOVE

UNITED STATES MAGISTRATE JUDGE

14JOINT CLAIM CONSTRUCTION CHART

Micron v. Tessera, No. 2:05-cv-319

15perimeter, said plurality of conductive elements connected to some of said plurality of conductive element pads on said second surface, said plurality of conductive elements having a second profile height of one of a height greater than said first profile height and a height substantially equal to said first profile height. 32. The stackable ball grid array package according to claim 30, wherein a first portion of said plurality of conductive elements aligns in a substantially parallel row having a first pitch spacing. 33. The stackable ball grid array package according to claim 32, wherein a second portion of said plurality of conductive elements aligns in a second parallel row having a second pitch spacing.

Claims 6 and 7

U.S. Patent No. 6,013,948

6. A stackable semiconductor package comprising: a substrate comprising a first surface, "substrate": "substrate": "substrate": an opposing second surface, and a cavity; [AGREED] [AGREED] A supporting material. a plurality of first contacts on the first surface; "cavity": "cavity": a plurality of second contacts on the second surface, the second contacts [AGREED] [AGREED] No construction. configured for electrically engaging third contacts substantially identical to the first contacts on a second semiconductor package substantially

18to the first surface to form a multi chip module.

Claims 1-3 and 10-11

U.S. Patent No. 5,107,328

1. A body for receiving a semiconductor die, said body comprising: "lid": "lid": a) a first shelf for receiving a lid; b) a second shelf having conductive [AGREED] [AGREED] No construction. traces thereon, said second shelf overlying a portion of the semiconductor die, wherein said traces couple with bond pads on the "second shelf having "second shelf having semiconductor die; conductive traces thereon, said conductive traces thereon, said c) a third shelf for receiving a base; and second shelf overlying a second shelf overlying a d) conductive leads for electrically portion of the semiconductor portion of the semiconductor coupling with an electronic device, die, wherein said traces couple die, wherein said traces couple wherein said conductive leads with bond pads on the with bond pads on the electrically couple with said semiconductor die": semiconductor die": conductive traces.

[AGREED] [AGREED] The second shelf, and the conductive traces on the second shelf, cover a portion of the semiconductor die wherein said traces electrically couple the bond pads on the semiconductor die and the conductive traces on the second shelf.

Tessera did not request separate "shelf": The parties both No construction. construction of “shelf” and agree that this term does not need “conductive traces” at the time to be construed separately. specified by PR 4-1 or PR 4-2. However, if the Court concludes that this term requires construction, the parties disagree

19as to how this term should be construed. Tessera believes that it should be construed to mean: A thin, flat, long, and narrow piece of material extending horizontally at a distance from a base to hold objects. See Tessera's Responsive Claim Construction Brief at 19-20. "conductive traces": The No construction. parties both agree that this term does not need to be construed separately. However, if the Court concludes that this term requires construction, the parties disagree as to how this term should be construed. Tessera believes that it should be construed to mean: Long strips of metal formed on the second shelf that connect one end of the bond wire to the conductive leads. See Tessera's Responsive Claim Construction Brief at 19-21

"base": "base": [AGREED] [AGREED] No construction.

20"conductive leads for "conductive leads for electrically coupling with an electrically coupling with an electronic device, wherein said electronic device, wherein said conductive leads electrically conductive leads electrically couple with said conductive couple with said conductive traces": traces": Conductive I/O elements on the An electrical conductor, made up Conductive leads: conductive outside of the body. of electrically conductive input/output (I/O) elements on

material, long and thin, not the outside of the body. shaped as a mass, used as No construction for the input/output (I/O) for connecting remainder of the disputed phrase. the package body to an external device. The conductive leads are connected to the conductive traces to provide an electrical current path between the leads and the traces.

2. The body of claim 1, wherein said second shelf contains a void, said void being located approximately above the bond pads of the semiconductor die, wherein a conductive material passes through said void to electrically couple said conductive traces with the bond pads on the semiconductor. 3. The body of claim 2, wherein said void bisects said second shelf. 10. The body of claim 1 wherein said body is manufactured from a material comprising plastic. 11. A logic component comprising: a) a "lid": "lid": semiconductor die; b) a body for receiving said semiconductor die; c) a [AGREED] [AGREED] No construction. lid and a base receivable by said body;

21d) a first shelf for receiving said lid; e) a second shelf having conductive traces "base": "base": thereon, said second shelf overlying a portion of the semiconductor die, [AGREED] [AGREED] No construction. wherein said traces couple with bond pads on the semiconductor die; f) a third shelf for receiving said base; and "second shelf having "second shelf having g) conductive leads for electrically conductive traces thereon, said conductive traces thereon, said coupling with an electronic device, second shelf overlying a second shelf overlying a wherein said conductive leads portion of the semiconductor portion of the semiconductor electrically couple with said die, wherein said traces couple die, wherein said traces couple conductive traces. with bond pads on the with bond pads on the

semiconductor die": semiconductor die": [AGREED] [Agreed] The second shelf, and the conductive traces on the second shelf, cover a portion of the semiconductor die wherein said traces electrically couple the bond pads on the semiconductor die and the conductive traces on the second shelf. Tessera did not request separate "shelf": The parties both agree No construction. construction of “shelf” and that this term does not need to be “conductive traces” at the time construed separately. However, specified by PR 4-1 or PR 4-2. if the Court concludes that this term requires construction, the parties disagree as to how this term should be construed. Tessera believes that it should be construed to mean: A thin, flat, long, and narrow piece of material extending horizontally at a

22distance from a base to hold objects. See Tessera's Responsive Claim Construction Brief at 19-20.

"conductive traces": The No construction. parties both agree that this term does not need to be construed separately. However, if the Court concludes that this term requires construction, the parties disagree as to how this term should be construed. Tessera believes that it should be construed to mean: Long strips of metal formed on the second shelf that connect one end of the bond wire to the conductive leads. See Tessera's Responsive Claim Construction Brief at 19-21

"conductive leads for "conductive leads for electrically coupling with an electrically coupling with an electronic device, wherein said electronic device, wherein said conductive leads electrically conductive leads electrically couple with said conductive couple with said conductive traces": traces": Conductive I/O elements on the An electrical conductor, made up Conductive leads: conductive outside of the body. of electrically conductive input/output (I/O) elements on

24substrate and said substrate, the plurality of electrical connectors connected to the plurality of circuit traces. 43. The electrical assembly of claim 35, where the die substrate comprises a printed circuit board.

Claims 1-2, 8, and 10-11

U.S. Patent No. Re 36,325

1. A memory array in which a This claim is not a Jepson This claim is a Jepson claim This claim is not a Jepson claim. plurality of memory circuit devices claim. wherein the preamble is are arranged in a manner such that admitted prior art, and all of The preamble of this claim is a memory information is obtained by The preamble of this claim is the elements set forth therein limitation as discussed in the addressing bits of information from a not a limitation. must be present in an accused Court’s claim construction selected number of the memory device to establish opinion. devices in the array in a format, and infringement. the format of bits forms a byte of memory data such that each byte includes bits from each memory device in the selected number of the circuit devices, and wherein the bits are addressed as rows and columns of information in a matrix on each memory device, characterized by: (a) a support structure which includes a single polymeric sheet, the polymeric sheet having a plurality of die receiving portions thereon, having tape automated bond (TAB) leads thereon and having a first set of electrical circuit traces on one side of the polymeric sheet, the tape automated bond pads being in electrical communication with the circuit traces; (b) a plurality of integrated circuitry memory devices, each device consisting of circuit elements

25deposited on a substrate and having conductive bumps deposited thereon, the integrated circuit devices being located within separate ones of the receiving portions of the single polymeric sheet, and connected to the polymeric sheet by being attached to the tape automated bond pads at the conductive bumps, and each of the integrated circuit devices being "means to mechanically "means to mechanically connected to the TAB leads on the stabilize the memory array so stabilize the memory array so polymeric sheet within its respective that the polymeric sheet, the that the polymeric sheet, the die receiving portion; memory devices and the circuit memory devices and the circuit (c) a second set of circuit traces on a terminals are maintained in terminals are maintained in plane which is separate from said one electrical communication electrical communication side of the polymeric sheet, the second during normal service" during normal service" set of circuit traces being in electrical communication with the first set of Claimed function: Claimed function: electrical circuit traces; (d) circuit terminals in electrical [AGREED] [AGREED] Claimed function: to communication with the circuit traces, mechanically stabilize the the circuit terminals configured in a memory array so that the pattern which conforms to a polymeric sheet, the memory predetermined external circuit devices and the circuit terminals connection and memory address are maintained in electrical protocol; and communication during normal (e) means to mechanically stabilize the service memory array so that the polymeric sheet, the memory devices and the Corresponding structure: Corresponding structure: Corresponding structure: circuit terminals are maintained in electrical communication during [AGREED] [AGREED] “Resin” normal service. 2. A memory array as defined in claim

1, further characterized by: the means to mechanically stabilize the memory array including mechanical structure which

26supports the circuit terminals. 8. A memory array as described in claim

1, characterized by: (a) each memory device having addresses which are arranged in similar matrices of rows and columns on the memory device; and (b) the addressing of a row of memory devices being accomplished to corresponding rows and columns on each memory device in a row of memory devices in response to address commands. 10. A memory array as described in claim 1, further characterized by: (a) the memory devices being random access memory semiconductor devices, having read and write address bits thereon; (b) the devices having row and column enable bits for the memory devices. 11. A memory array as described in claim 1, further characterized by: the memory devices being dynamic random access memories.

Claims 1, 2, 8, 10-11

U.S. Patent No. 4,992,849

1. Board level integrated circuit in This claim is not a Jepson This claim is a Jepson claim This claim is not a Jepson claim. which a plurality of semiconductor claim. wherein the preamble is circuit devices are arranged on a admitted prior art, and all of The preamble of this claim is a flexible circuit board and each of the The preamble of this claim is the elements set forth therein limitation as discussed in the semiconductor circuit devices is a not a limitation. must be present in an accused Court’s claim construction distinct integrated circuit chip, device to establish opinion. characterized by: infringement. (a) a support structure which includes a single polymeric sheet, the polymeric

27sheet having a plurality of die receiving portions thereon, having tape automated bond (TAB) pads thereon and having a first set of electrical circuit traces on one side of the polymeric sheet, the tape automated bond pads being in electrical communication with the circuit traces; (b) the plurality of integrated circuit devices each consisting of circuit elements deposited on a substrate and having conductive bumps deposited thereon, the integrated circuit devices being located within separate ones of the die receiving portions of the single polymeric sheet, mounted to the polymeric sheet and connected to the "means to mechanically "means to mechanically polymeric sheet by being attached to stabilize the polymeric sheet stabilize the polymeric sheet the tape automated bond pads at the with the integrated circuit with the integrated circuit conductive bumps, and each of the devices mounted thereon so devices mounted thereon so integrated circuit devices being that the polymeric sheet, the that the polymeric sheet, the connected to the TAB leads on the integrated circuit devices and integrated circuit devices and polymeric sheet within its respective the circuit terminals are the circuit terminals are die receiving portion; maintained in electrical maintained in electrical (c) a second set of circuit traces on a communication during normal communication during normal plane which is separate from said one service" service" side of the polymeric sheet, the second set of circuit traces being in electrical Claimed function: Claimed function: communication with the first set of electrical circuit traces; [AGREED] [AGREED] Claimed function: to (d) circuit terminals in electrical mechanically stabilize the communication with the circuit traces, polymeric sheet with the the circuit terminals configured in a integrated circuit devices pattern which conforms to a mounted thereon so that the predetermined external circuit polymeric sheet, the integrated connection protocol; and circuit devices and the circuit28 (e) means to mechanically stabilize the terminals are maintained in polymeric sheet with the integrated electrical communication during circuit devices mounted thereon so normal service. that the polymeric sheet, the integrated circuit devices and the Corresponding structure: Corresponding structure: Corresponding structure: circuit terminals are maintained in electrical communication during [AGREED] [AGREED] “Resin” normal service. 2. Board level integrated circuit as defined in claim 1, further characterized by: the means to mechanically stabilize the board level integrated circuit including mechanical structure which supports the circuit terminals. 8. Board level integrated circuit as described in claim 1, characterized by: (a) a group of the integrated circuit "a group of the integrated "a group of the integrated "a group of the integrated devices having addresses which are circuit devices": circuit devices": circuit devices": arranged in similar matrices of rows and columns on the integrated circuit [AGREED] [AGREED] Two or more integrated circuit device; and devices. (b) the addressing of a row of integrated circuit devices in the group being accomplished to corresponding rows and columns on each integrated circuit device in a row of integrated circuit devices in the group in response to address commands. 10. Board level integrated circuit as described in claim 9, further characterized by: the integrated circuit devices being dynamic random access memories. 11. Board level integrated circuit as described in claim 1, further characterized by:

29a group of the integrated circuit "a group of the integrated "a group of the integrated "a group of the integrated devices being random access memory circuit devices": circuit devices": circuit devices": semiconductor devices, having read and write address bits thereon, having [AGREED] [AGREED] Two or more integrated circuit row and column enable bits for the devices. memory devices.